Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 11881862 | Mitigation of duty-cycle distortion | Udayakiran Kumar Yallamaraju, Xia Li, Pankaj Deshmukh, Vajram Ghantasala, Bin Yang +4 more | 2024-01-23 | $18,184,000 |
| 11327525 | Clock monitoring unit with serial clock routing pipeline | Federico Salluzzo, Sina Dena, Amod Phadke | 2022-05-10 | $16,114,000 |