Issued Patents All Time
Showing 26–50 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10101798 | Reducing power consumption in a server cluster | Minwen Ji, Timothy P. Mann, Tahir Mobashir, Umit Rencuzogullari, Ganesha Shanmuganathan +2 more | 2018-10-16 |
| 10049006 | Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands | David G. Reed | 2018-08-14 |
| 10020036 | Address bit remapping scheme to reduce access granularity of DRAM accesses | Wishwesh Anil Gandhi, Ram Gummadi | 2018-07-10 |
| 9973879 | Opportunistic decoding of transmissions on a forward link in a machine-to-machine wireless wide area network | Bin Tian | 2018-05-15 |
| 9881662 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2018-01-30 |
| 9880900 | Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state | David G. Reed | 2018-01-30 |
| 9830958 | Time-multiplexed communication protocol for transmitting a command and address between a memory controller and multi-port memory | — | 2017-11-28 |
| 9828652 | Highly formable automotive aluminum sheet with reduced or no surface roping and a method of preparation | Rajeev G. Kamat, David Michael Custers, Aude Despois | 2017-11-28 |
| 9823964 | Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation | David G. Reed | 2017-11-21 |
| 9646656 | Time-multiplexed communication protocol for transmitting a command and address between a memory controller and multi-port memory | — | 2017-05-09 |
| 9552865 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2017-01-24 |
| 9408172 | High precision network synchronization in an indoor position location system | — | 2016-08-02 |
| 9363776 | High precision access point to access point synchronization in an indoor position location system | William E. Stein, Scott Howard King | 2016-06-07 |
| 9361254 | Memory device formed with a semiconductor interposer | — | 2016-06-07 |
| 9338034 | Ternary sequences with power of two exponent dimensionalities suitable for channel estimation | Siavash Ekbatani | 2016-05-10 |
| 9330031 | System and method for calibration of serial links using a serial-to-parallel loopback | — | 2016-05-03 |
| 9285827 | Systems and methods for optimizing data storage among a plurality of solid state memory subsystems | Jason Breakstone, Himanshu Desai, Angelo Campos | 2016-03-15 |
| 9263103 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2016-02-16 |
| 9263106 | Efficient command mapping scheme for short data burst length memory devices | — | 2016-02-16 |
| 9232524 | Multiple access scheme for multi-channels of a network with a limited link budget | Bin Tian | 2016-01-05 |
| 9226289 | Systems and methods to conserve power of machine-to-machine devices using a shared data channel | Bin Tian | 2015-12-29 |
| 9179409 | Multiple access scheme for narrowband channels | Bin Tian, Ethan Lin | 2015-11-03 |
| 9177632 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2015-11-03 |
| 9165638 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2015-10-20 |
| 9142281 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Ian Shaeffer, Steven C. Woo | 2015-09-22 |