Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10019380 | Providing memory management functionality using aggregated memory management units (MMUs) | Serag Gadelrab, Jason Edward Podaima, Ruolong Liu, Paul Christopher John Wiercienski, Kyle John Ernewein +4 more | 2018-07-10 |
| 10007619 | Multi-threaded translation and transaction re-ordering for memory management units | Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Meghal Varia, Kyle John Ernewein +3 more | 2018-06-26 |
| 9836410 | Burst translation look-aside buffer | Jason Edward Podaima, Paul Christopher John Wiercienski | 2017-12-05 |
| 9824015 | Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media | Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Gadelrab, Paul Christopher John Wiercienski +1 more | 2017-11-21 |
| 7849256 | Memory controller with ring bus for interconnecting memory clients to memory devices | Warren Fritz Kruger, Patrick Law | 2010-12-07 |
| 7657774 | Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board | Eric Hung, Geeta Desai, Vijendra Kuroodi, Mirko Vojnovic | 2010-02-02 |
| 7409572 | Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board | Eric Hung, Geeta Desai, Vijendra Kuroodi, Mirko Vojnovic | 2008-08-05 |
| 6647462 | Apparatus and a method for providing decoded information | Vitaly Sukonik, Amit Dor, Rami Natan | 2003-11-11 |
| 6553487 | Device and method for performing high-speed low overhead context switch | Vitaly Sukonik, Amit Dor | 2003-04-22 |