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Providing memory management functionality using aggregated memory management units (MMUs) |
Serag Gadelrab, Jason Edward Podaima, Ruolong Liu, Paul Christopher John Wiercienski, Kyle John Ernewein +4 more |
2018-07-10 |
| 10007619 |
Multi-threaded translation and transaction re-ordering for memory management units |
Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Meghal Varia, Kyle John Ernewein +3 more |
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| 9836410 |
Burst translation look-aside buffer |
Jason Edward Podaima, Paul Christopher John Wiercienski |
2017-12-05 |
| 9824015 |
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media |
Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Gadelrab, Paul Christopher John Wiercienski +1 more |
2017-11-21 |
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Memory controller with ring bus for interconnecting memory clients to memory devices |
Warren Fritz Kruger, Patrick Law |
2010-12-07 |
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Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board |
Eric Hung, Geeta Desai, Vijendra Kuroodi, Mirko Vojnovic |
2010-02-02 |
| 7409572 |
Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board |
Eric Hung, Geeta Desai, Vijendra Kuroodi, Mirko Vojnovic |
2008-08-05 |
| 6647462 |
Apparatus and a method for providing decoded information |
Vitaly Sukonik, Amit Dor, Rami Natan |
2003-11-11 |
| 6553487 |
Device and method for performing high-speed low overhead context switch |
Vitaly Sukonik, Amit Dor |
2003-04-22 |
