Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols

Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols

US Patent 9990291 · Granted Jun 5, 2018

Estimated economic value: $12,691,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Transaction requests according to a request ordering protocol2025
Eddy current monitoring to detect vibration in polishing2025
Physically aware design of interconnect fabric2025
Smart mirror2025
Polishing apparatus using machine learning and compensation for pad thickness2025
Coring and sampling integrated sub and downhole instrument2025
Integral pulp-molded bottle, mold for molding integral pulp-molded bottle, appar2025
Gradient compression for distributed training2025
Resistivity-based adjustment of thresholds for in-situ monitoring2025
Sparse machine learning acceleration2025
Method and device for induced localized electrodeposition on back side of thin-w2025
Strong ordered transaction for DMA transfers2025