Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits

Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits

US Patent 9947419 · Granted Apr 17, 2018

Estimated economic value: $5,906,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

On chip test architecture for continuous time delta sigma analog-to-digital conv2025
Apparatuses and methods for facilitating solutions to optimization problems via 2025
Memory with scan chain testing of column redundancy logic and multiplexing2025
Routing and regenerator planning in a carrier's core reconfigurable optical netw2025
Low overhead mesochronous digital interface2025
High-speed multi-port memory supporting collision2024
Method and system for managing service quality according to network status predi2024
Bias current receiver with selective coupling circuit2024
Conflict-free change deployment2024
Power supply circuit with reduced leakage current2024
Memory circuit architecture with multiplexing between memory banks2024
Spatial light modulators2024