Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

US Patent 9904758 · Granted Feb 27, 2018

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method of analyzing integrated circuit in consideration of a process 2022
Method for reducing power consumption in scannable flip-flops without additional2021
Low-power low-setup integrated clock gating cell with complex enable selection2020
Power rail for standard cell block2020
Power rail for standard cell block2020
Low power integrated clock gating system and method2020
Power grid and standard cell co-design structure and methods thereof2020
Power grid and standard cell co-design structure and methods thereof2020
System and method for improving scan hold-time violation and low voltage operati2020
Layout connection isolation technique for improving immunity to jitter and volta2020
High speed domino-based flip flop2020
Integrated circuit including cells/gates arranged based on supply voltage variat2019