{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Instruction and logic for reducing data cache evictions in an out-of-order processor", "item": "https://www.patentleaderboard.com/patent/9870209"}]}

Home › Instruction and logic for reducing data cache evictions in an out-of-order processor

Instruction and logic for reducing data cache evictions in an out-of-order processor

US Patent 9870209 · Granted Jan 16, 2018

Estimated economic value: $17,139,000 ⓘ

Assignee

Intel

Inventors

John H. Kelm (24 patents)
Demos Pavlou (8 patents)
Mirem Hyuseinova (5 patents)

View full patent text on Google Patents →