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Home › Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias

Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias

US Patent 9836399 · Granted Dec 5, 2017

Estimated economic value: $17,379,000 ⓘ

Assignee

Intel

Inventors

Krishna N. Vinod (6 patents)
Avinash Sodani (75 patents)
Zainulabedin J. Aurangabadwala (2 patents)

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