Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods, apparatus and system for providing NMOS-only memory cells

Methods, apparatus and system for providing NMOS-only memory cells

US Patent 9799393 · Granted Oct 24, 2017

Estimated economic value: $9,961,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Compact memory-in-pixel display structure2025
Memory built-in self-test with automated reference trim feedback for memory sens2024
Memory built-in self-test with automated multiple step reference trimming2024
Reference bits test and repair using memory built-in self-test2024
Pre-compare operation for compact low-leakage dual-compare cam cell2024
Compact low-leakage multi-bit compare CAM cell2023
SRAM bit cells formed with dummy structures2021
Semiconductor structure including a ferroelectric transistor and method for the 2017
Semiconductor structure including a ferroelectric transistor and method for the 2016
Method and apparatus for bit-line sensing gates on an SRAM cell2015
Clocked memory with latching predecoder circuitry2014
Mismatch verification device and methods thereof2014