Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

US Patent 9734920 · Granted Aug 15, 2017

Estimated economic value: $1,588,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Reliable electronic fuse based storage using error correction coding2025
Built-in self-test (BIST) engine configured to store a per pattern based fail st2022
Memory bypass function for a memory2021
Built-in self-test (BIST) engine configured to store a per pattern based fail st2021
Built-in self-test (BIST) engine configured to store a per pattern based fail st2020
Memory bypass function for a memory2020
Method and system for enumerating digital circuits in a system-on-a-chip (SOC)2020
Method and system for enumerating digital circuits in a system-on-a-chip (SOC)2020
Arbitration for memory diagnostics2020
Arbitration for memory diagnostics2020
Built-in self-test (BIST) engine configured to store a per pattern based fail st2020
Memory built-in self-test (MBIST) test time reduction2019