{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Reduced PTH pad for enabling core routing and substrate layer count reduction", "item": "https://www.patentleaderboard.com/patent/9711441"}]}
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Home › Reduced PTH pad for enabling core routing and substrate layer count reduction

Reduced PTH pad for enabling core routing and substrate layer count reduction

US Patent 9711441 · Granted Jul 18, 2017

Estimated economic value: $6,909,000 ⓘ

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