Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Pattern placement error compensation layer

Pattern placement error compensation layer

US Patent 9704807 · Granted Jul 11, 2017

Estimated economic value: $13,027,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Polarization-multiplexed radiator system, light source system, and method of ope2024
Uniformity control of metal-based photoresists2021
Radial lithographic source homogenizer2020
Automated redesign of integrated circuits using relaxed spacing rules2020
Balancing collector contamination of a light source by selective deposition2019
Devices and methods for forming cross coupled contacts2019
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2019
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2018
Method, apparatus and system for using free-electron laser compatible EUV beam f2017
Self-aligned conductive polymer pattern placement error compensation layer2017
Self-aligned conductive polymer pattern placement error compensation layer2017
Pattern placement error compensation layer in via opening2017