Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion

Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion

US Patent 9647205 · Granted May 9, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electron block frame pouring fixture2021
Method for concurrent system management and error detection and correction reque2016
Integrated circuit shielding technique utilizing stacked die technology incorpor2015
Integrated circuit shielding technique utilizing stacked die technology incorpor2015
Integrated circuit shielding technique utilizing stacked die technology incorpor2015
Integrated circuit shielding technique utilizing stacked die technology incorpor2015
Independent orthogonal error correction and detection2014
Tungsten stiffener for flexible substrate assembly2012
Temperature insensitive reference circuit for use in a voltage detection circuit2010
SET and SEGR resistant delay cell and delay line for Power-On Reset circuit appl2010
Radiation hardened logic circuit2008
Five volt tolerant and fail safe input scheme using source follower configuratio2004