Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

US Patent 9519442 · Granted Dec 13, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit shielding technique utilizing stacked die technology incorpor2017
Voltage regulator for systems with a high dynamic current range2016
Method for creating a reliable phase-locked loop in a ruggedized or harsh enviro2016
Method for creating a reliable phase-locked loop in a ruggedized or harsh enviro2016
Method for synchronizing a multiplicity of clock generating circuits2016
Method for synchronizing a multiplicity of clock generating circuits2016
Integrated circuit shielding technique utilizing stacked die technology incorpor2015
Independent orthogonal error correction and detection2014
Independent orthogonal error correction and detection2014
N-bit shift register controller2011
Temperature insensitive reference circuit for use in a voltage detection circuit2010
SET and SEGR resistant delay cell and delay line for Power-On Reset circuit appl2010