Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

US Patent 9634138 · Granted Apr 25, 2017

Estimated economic value: $8,459,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Leakage current reduction in polysilicon-on-active-edge structures2022
SRAM source-drain structure2021
SRAM source-drain structure2021
Sensor for gate leakage detection2021
Integration of finFET device2021
Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) fo2020
Systems and methods for fabrication of gated diodes with selective epitaxial gro2020
Reducing or avoiding mechanical stress in static random access memory (SRAM) str2019
Reducing or avoiding mechanical stress in static random access memory (SRAM) str2019
FinFET with reduced series total resistance2019
FinFET with reduced series total resistance2019
Field-effect transistor (FET) devices employing adjacent asymmetric active gate 2018