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Home › Methods for fabricating integrated circuits using directed self-assembly including a substantially periodic array of topographical features that includes etch resistant topographical features for transferability control

Methods for fabricating integrated circuits using directed self-assembly including a substantially periodic array of topographical features that includes etch resistant topographical features for transferability control

US Patent 9530662 · Granted Dec 27, 2016

Estimated economic value: $8,113,000 ⓘ

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