Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fully-depleted silicon-on-insulator transistors

Fully-depleted silicon-on-insulator transistors

US Patent 9520329 · Granted Dec 13, 2016

Estimated economic value: $6,265,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High aspect ratio contact structure with multiple metal stacks2025
Size-efficient mitigation of latchup and latchup propagation2025
Semiconductor device design mitigating latch-up2024
Long channel and short channel vertical FET co-integration for vertical FET VTFE2024
Heat pipe for vertically stacked field effect transistors2024
Gate-all-around field effect transistor having multiple threshold voltages2024
Latch-up avoidance for sea-of-gates2023
Fully depleted SOI transistor with a buried ferroelectric layer in back-gate2023
Semiconductor on insulator structure comprising a buried high resistivity layer2022
Methods of performing fin cut etch processes for FinFET semiconductor devices2022
Multi-metal dipole doping to offer multi-threshold voltage pairs without channel2022
Nanosheet field effect transistors with partial inside spacers2022