Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Techniques to reduce memory cell refreshes for a memory device

Techniques to reduce memory cell refreshes for a memory device

US Patent 9418723 · Granted Aug 16, 2016

Estimated economic value: $10,311,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Computer architecture for generating an integrated data repository2025
Memory circuit and write method2025
Systems and methods for classifying puf signature modules of integrated circuits2025
Systems and methods to store multi-level data2025
Integrated circuit (IC) signatures with random number generator and one-time pro2025
Technologies for memory and I/O efficient operations on homomorphically encrypte2025
Integrated circuit layout, integrated circuit, and method for fabricating the sa2025
Buffer control of multiple memory banks2025
Physical unclonable function (PUF) security key generation2025
Method and apparatus for protecting a PUF generator2025
Method for PUF generation using variations in transistor threshold voltage and s2025
Integrated circuit and method of operating same2025