Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Zoned erase verify in three dimensional nonvolatile memory

Zoned erase verify in three dimensional nonvolatile memory

US Patent 9312026 · Granted Apr 12, 2016

Estimated economic value: $17,057,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for programming a memory device to reduce retention error2025
Enhanced gradient seeding scheme during a program operation in a memory sub-syst2025
Selective increase and decrease to pass voltages for programming a memory device2025
Bias voltage schemes during pre-programming and programming phases2025
Memory device having memory cell strings and separate read and write control gat2025
Method for programming memory device to reduce retention error2024
Detrapping electrons to prevent quick charge loss during program verify operatio2024
Electronic devices comprising reduced charge confinement regions in storage node2024
Linked XOR flash data protection scheme2024
Enhanced gradient seeding scheme during a program operation in a memory sub-syst2024
Distributed compaction of logical states to reduce program time2023
Short program verify recovery with reduced programming disturbance in a memory s2023