Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods

Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods

US Patent 11956954 · Granted Apr 9, 2024

Estimated economic value: $33,276,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microelectronic devices with source region vertical extension between upper and 2025
Microelectronic devices including stack structures having doped interfacial regi2025
Microelectronic devices including stack structures having doped interfacial regi2025
Method and device for automatically locking repetition frequency and carrier-env2025
Apparatus and method for rapid cooling of high temperature gas2025
Microelectronic devices with vertically recessed channel structures and discrete2025
Calculation method for fractal dimension of shale pores2025
Quantitative prediction method for gas content of deep marine shale2025
Apparatuses including band offset materials, and related memory devices2025
Microelectronic devices including pillars with partially-circular upper portions2025
Enhanced gradient seeding scheme during a program operation in a memory sub-syst2025
Selective increase and decrease to pass voltages for programming a memory device2025