Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Non-systematic coded error correction

Non-systematic coded error correction

US Patent 9229802 · Granted Jan 5, 2016

Estimated economic value: $5,653,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Layout for dual in-line memory to support 128-byte cache line processor2025
Techniques for managed NAND translation with embedded memory systems2024
Stopping criteria for layered iterative error correction2022
Stopping criteria for layered iterative error correction2021
Memory devices having differently configured blocks of memory cells2021
Memory devices having differently configured blocks of memory cells2021
Dual-sided memory module with channels aligned in opposition2020
State change in systems having devices coupled in a chained configuration2020
Chained bus memory device2020
Memory devices having differently configured blocks of memory cells2019
Dual-sided memory module with channels aligned in opposition2019
Stopping criteria for layered iterative error correction2019