Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of increasing a timing margin for relaying data to a memory array

Method of increasing a timing margin for relaying data to a memory array

US Patent 8988967 · Granted Mar 24, 2015

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory apparatus and signal delay circuit for generating delayed column select s2014
Synchronous signal generating circuit2013
Method of increasing a timing margin for writing data to a memory array2012
Method of increasing a timing margin for writing data to a memory array2012
Apparatus and method for controlling delay stage of off-chip driver2012
Low power synchronous memory command address scheme2011
External compensation for input current source2011
Method to reduce variation in CMOS delay2010
OCD driver slew rate control2010
Temperature and supply-voltage sensing circuit1997
Memory device performance by delayed power-down1997
Array-source line, bitline and wordline sequence in flash operations1997