Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Device structure, layout and fabrication method for uniaxially strained transistors

Device structure, layout and fabrication method for uniaxially strained transistors

US Patent 8933515 · Granted Jan 13, 2015

Estimated economic value: $4,389,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertically stacked FET with strained channel2025
Nanowire source/drain formation for nanosheet device2025
In-situ chip design for pulse IV self-heating evaluation2025
Strain generation and anchoring in gate-all-around field effect transistors2025
Buried power rail with robust connection to a wrap around contact2025
Conductive oxide diffusion barrier for laser crystallization2025
Semiconductor structure with wrapped-around backside contact2025
Two-dimensional vertical fins2025
Aluminum oxide protected lithium metal tunable 3D silicon batteries2025
Gain cell memory based physically unclonable function2025
Air gap spacer for metal gates2025
Stacked cross-point phase change memory2025