Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for congestion-aware routing in a computer interconnection network

Method and apparatus for congestion-aware routing in a computer interconnection network

US Patent 8694704 · Granted Apr 8, 2014

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Branch target buffer arrangement with preferential storage for unconditional bra2023
Packed error correction code (ECC) for compressed data protection2022
Methods, systems, and computer readable media for performing page fault handling2022
Branch target buffer for a data processing apparatus2022
Atomic object reads for in-memory rack-scale computing2021
Unified prefetching into instruction cache and branch target buffer2018
Scale-out non-uniform memory access2017
Network-on-chip using request and reply trees for low-latency processor-memory c2017
Method and apparatus for congestion-aware routing in a computer interconnection 2017
Method and apparatus for congestion-aware routing in a computer interconnection 2017
Scalable bus-based on-chip interconnection networks2012
Method and apparatus for congestion-aware routing in a computer interconnection 2012