Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Scalable bus-based on-chip interconnection networks

Scalable bus-based on-chip interconnection networks

US Patent 8307116 · Granted Nov 6, 2012

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Efficient neural network accelerator dataflows2025
Hierarchical network for stacked memory system2025
Single-cycle byte correcting and multi-byte detecting error code2024
System and methods for hardware-software cooperative pipeline error detection2024
Application partitioning for locality in a stacked memory system2024
Adversarial scenarios for safety testing of autonomous vehicles2024
Hierarchical network for stacked memory system2024
Deep neural network accelerator with fine-grained parallelism discovery2024
Sparse convolutional neural network accelerator2023
Scalable multi-die deep learning system2023
Techniques for configuring parallel processors for different application domains2023
Adversarial scenarios for safety testing of autonomous vehicles2023