Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor

Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor

US Patent 8691644 · Granted Apr 8, 2014

Estimated economic value: $5,421,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Automated training and selection of models for document analysis2024
Representing documents using document keys2023
NPN heterojunction bipolar transistor in CMOS flow2022
Representing documents using document keys2022
Risk prediction based on automated analysis of documents2021
Low temperature sub-nanometer periodic stack dielectrics2021
Automated training and selection of models for document analysis2021
Replacement metal gate process for CMOS integrated circuits2020
Risk prediction based on automated analysis of documents2020
Lubricant dispersed with carbon nanotubes2020
Integrated circuit having chemically modified spacer surface2019
Clause discovery for validation of documents2019