Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations

Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations

US Patent 8587288 · Granted Nov 19, 2013

Estimated economic value: $3,686,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

CFET with independent gate control and low parasitic capacitance2025
Different dimensions across active region for stronger via to backside power rai2025
Static random access memory device with stacked FETs2025
Multi-level programming of phase change memory device2025
Local enlarged via-to-backside power rail2025
High density static random-access memory2025
Metal lines with low via-to-via spacing2025
Stacked cross-point phase change memory2025
Forming self-aligned vias and air-gaps in semiconductor fabrication2025
Electronic devices with a low dielectric constant2025
Hybrid gate cut for stacked transistors2025
Stacked layer memory suitable for SRAM and having a long cell2025