Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model

Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model

US Patent 8484007 · Granted Jul 9, 2013

Estimated economic value: $6,470,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Identifying security vulnerabilities using modeled attribute propagation2023
Targeted very long delay for increasing speculative execution progression2022
Identifying microarchitectural security vulnerabilities using simulation compari2021
Memory blockade for verifying system security with respect to speculative execut2021
Acceleration of memory walking sequences during simulation2019
Implementing processor functional verification by generating and running constra2017
Implementing processor functional verification by generating and running constra2017
Exiting multiple threads of a simulation environment in a computer2016
Firmware and hardware verification using Opcode comparison2015
Method, system and computer program product for verifying address generation, in2012
Method, system, and computer program product for out of order instruction addres2011
System and method for providing a common instruction table2011