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Home › Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

US Patent 8468483 · Granted Jun 18, 2013

Estimated economic value: $7,677,000 ⓘ

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