Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and methods of reducing pre-emphasis voltage jitter

Apparatus and methods of reducing pre-emphasis voltage jitter

US Patent 8446172 · Granted May 21, 2013

Estimated economic value: $30,555,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Noise attenuation panel2023
High-speed serial data signal receiver circuitry2018
Backchannel transmission adaptation2018
High-speed serial data signal receiver circuitry2017
Multimode equalization circuitry2017
Multimode current mirror circuitry2016
Apparatus and method for sense amplifier offset cancellation2016
Receiver eye-monitor circuit and method2016
Adaptations for partial response summation node embedded FPGA transceiver2016
Pre-emphasis circuitry including a pre-emphasis voltage variation compensation e2016
Pre-emphasis circuitry including a pre-emphasis voltage variation compensation e2016
Transceiver circuitry with summation node common mode droop reduction2016