Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transformation of IC designs for formal verification

Transformation of IC designs for formal verification

US Patent 8443317 · Granted May 14, 2013

Estimated economic value: $5,105,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power-efficient enable signal for fanin-based sequential clock gating on enabled2024
Providing guidance to an equivalence checker when a design contains retimed regi2020
Providing guidance to an equivalence checker when a design contains retimed regi2020
Multi-bit-mapping aware clock gating2018
Transformation of IC designs for formal verification2013
Transformation of IC designs for formal verification2013
Computed tomography apparatus and method for classifying objects2001
Apparatus and method for optimizing detection of objects in computed tomography 2001
Architecture for CT scanning system2001
Apparatus and method for combining related objects in computed tomography data2000
Apparatus and method for detecting sheet objects in computed tomography data2000
Apparatus and method for correcting object density in computed tomography data2000