Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10628545 | Providing guidance to an equivalence checker when a design contains retimed registers | Muzaffer Hiraoglu, Darren Charles Cronquist, Navneet Kakkar, Sridhar Keladi | 2020-04-21 |
| 10157253 | Multi-bit-mapping aware clock gating | Wladimir Alejandro Plagges Martinez, Reiner Wilhelm Genevriere | 2018-12-18 |
| 8453083 | Transformation of IC designs for formal verification | Muzaffer Hiraoglu | 2013-05-28 |
| 8443317 | Transformation of IC designs for formal verification | Muzaffer Hiraoglu | 2013-05-14 |