{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Advisory system for verifying sensitive circuits in chip-design", "item": "https://www.patentleaderboard.com/patent/8418098"}]}
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Home › Advisory system for verifying sensitive circuits in chip-design

Advisory system for verifying sensitive circuits in chip-design

US Patent 8418098 · Granted Apr 9, 2013

Estimated economic value: $4,980,000 ⓘ

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