Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Verification of 3D integrated circuits

Verification of 3D integrated circuits

US Patent 8359554 · Granted Jan 22, 2013

Estimated economic value: $8,054,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor structure including boundary header cell and method for manufactur2025
Integrated circuit and method of forming the same2025
Structure and method of rectangular cell in semiconductor device2025
Diagonal torus network2025
Integrated circuit device and method2025
Integrated circuit stack verification method and system for performing the same2025
Systems and methods for integrated circuit layout2025
Conductive line structures and method of forming same2025
Integrated circuit with mixed row heights2025
Semiconductor arrangement and method of making2025
Semiconductor device including standard-cell-adapted power grid arrangement2024
Systems and methods for context aware circuit design2024