Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of reducing coupling between floating gates in nonvolatile memory

Method of reducing coupling between floating gates in nonvolatile memory

US Patent 8288225 · Granted Oct 16, 2012

Estimated economic value: $11,494,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three-dimensional memory device including laterally separated source lines and m2025
Memory device including composite metal oxide semiconductor channels and methods2025
Non-volatile memory with inter-die connection2025
Bonded assembly including interconnect-level bonding pads and methods of forming2025
Three-dimensional nor array and method of making the same2025
Three-dimensional nor array and method of making the same2025
Three dimensional memory device containing resonant tunneling barrier and high m2025
Three dimensional memory device containing resonant tunneling barrier and high m2025
Methods and apparatuses for forming semiconductor devices containing tungsten la2025
Three dimensional memory device containing resonant tunneling barrier and high m2025
Three-dimensional memory array with dual-level peripheral circuits and methods f2025
Methods and apparatuses for forming semiconductor devices containing tungsten la2024