Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for forming a nonvolatile memory cell comprising a reduced height vertical diode

Method for forming a nonvolatile memory cell comprising a reduced height vertical diode

US Patent 8252644 · Granted Aug 28, 2012

Estimated economic value: $16,101,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Thin film storage transistor with silicon oxide nitride charge trapping layer2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Vertical thin-film transistor and application as bit-line connector for 3-dimens2025
Methods for forming multilayer horizontal NOR-type thin-film memory strings2025
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensio2025
Methods for forming multi-layer vertical NOR-type memory string arrays2024
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2024
3-dimensional NOR memory array with very fine pitch: device and method2024
Staggered word line architecture for reduced disturb in 3-dimensional nor memory2024
Thin-film storage transistors in a 3-dimensional array of nor memory strings and2024
Memory device including modular memory units and modular circuit units for concu2024
Process for forming a vertical thin-film transistor that serves as a connector t2024