Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Three-dimensional transistor with double channel configuration

Three-dimensional transistor with double channel configuration

US Patent 8164145 · Granted Apr 24, 2012

Estimated economic value: $12,212,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for forming a strained transistor by stress memorization based on a stres2015
Transistor with embedded strain-inducing material formed in diamond-shaped cavit2014
Fabrication of a semiconductor device with extended epitaxial semiconductor regi2014
Semiconductor devices having encapsulated isolation regions and related fabricat2013
Body controlled double channel transistor and circuits comprising the same2013
Method for differential spacer removal by wet chemical etch process and device w2012
Static RAM cell design and multi-contact regime for connecting double channel tr2012
Static RAM cell design and multi-contact regime for connecting double channel tr2012
Semiconductor device comprising isolation trenches inducing different types of s2012
Method of forming a semiconductor structure comprising a formation of at least o2011
Method for forming a strained transistor by stress memorization based on a stres2011
Method for selectively forming strain in a transistor by a stress memorization t2011