Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of forming silicon oxides and methods of forming interlevel dielectrics

Methods of forming silicon oxides and methods of forming interlevel dielectrics

US Patent 8105956 · Granted Jan 31, 2012

Estimated economic value: $5,143,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Slit stress modulation in semiconductor substrates2020
Methods of forming an elevationally extending conductor laterally between a pair2018
Slit stress modulation in semiconductor substrates2018
Array of conductive vias, methods of forming a memory array, and methods of form2017
Methods of forming an elevationally extending conductor laterally between a pair2017
Array of conductive vias, methods of forming a memory array, and methods of form2017
Methods of forming electrically conductive lines2015
Electrically conductive lines and integrated circuitry comprising a line of rece2015
Integrated circuit devices and methods of forming memory array and peripheral ci2013
Methods of forming an electrically conductive buried line and an electrical cont2013
Integrated circuit devices and methods of forming memory array and peripheral ci2013
Methods of forming silicon oxides and methods of forming interlevel dielectrics2013