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Home › Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation

Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation

US Patent 8021950 · Granted Sep 20, 2011

Estimated economic value: $5,575,000 ⓘ

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