Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

US Patent 8001437 · Granted Aug 16, 2011

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Virtual object control method and apparatus, terminal, and storage medium2025
Test pattern generation device, fault detection system, test pattern generation 2017
Method and apparatus for broadcasting scan patterns in a scan-based integrated c2017
Multiple-capture DFT method for detecting or locating crossing clock-domain faul2017
Fault detection system, generation circuit, and program2016
Fault detection system, generation circuit, and program2016
Semiconductor device, detection method and program2016
Multiple-capture DFT system for detecting or locating crossing clock-domain faul2016
Multiple-capture DFT system for detecting or locating crossing clock-domain faul2016
Multiple-capture DFT system for detecting or locating crossing clock-domain faul2015
Fault detection system, acquisition apparatus, fault detection method, program, 2015
Computer-aided design system to automate scan synthesis at register-transfer lev2014