Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for improving CMOS compatible non volatile memory retention reliability

System and method for improving CMOS compatible non volatile memory retention reliability

US Patent 7910420 · Granted Mar 22, 2011

Estimated economic value: $2,634,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hybrid switch circuit with bidirectional double-base bipolar junction transistor2025
Methods and systems of operating a double-sided double-base bipolar junction tra2025
Unidirectional hybrid switch circuit2025
System and method for bi-directional trench power switches2024
Semiconductor device with bi-directional double-base trench power switches2024
High voltage vertical semiconductor device with multiple pillars in a racetrack 2018
Configuration and fabrication of semiconductor structure using empty and filled 2014
Structure and method for post oxidation silicon trench bottom shaping2014
Non-volatile memory cell with asymmetrical split gate and related system and met2013
Method and apparatus for reducing plasma process induced damage in integrated ci2013
High-performance CMOS-compatible non-volatile memory cell and related method2012
System and method for providing low voltage high density multi-bit storage flash2012