Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and structure for forming multiple self-aligned gate stacks for logic devices

Method and structure for forming multiple self-aligned gate stacks for logic devices

US Patent 7790541 · Granted Sep 7, 2010

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Wearable device for monitoring bodily fluids2025
Bulk nanosheet with dielectric isolation2025
PVD tool to deposit highly reactive materials2025
MRAM stack with reduced height2025
Structure and process to tuck fin tips self-aligned to gates2024
Half buried nFET/pFET epitaxy source/drain strap2023
Double magnetic tunnel junction device2023
Dielectric isolated fin with improved fin profile2023
High retention eMRAM using VCMA-assisted writing2023
Wrap-around bottom contact for bottom source/drain2023
Magnetoresistive random-access memory device2023
MJT based anti-fuses with low programming voltage2023