Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Avoiding livelock using intervention messages in multiple core processors

Avoiding livelock using intervention messages in multiple core processors

US Patent 7769958 · Granted Aug 3, 2010

Estimated economic value: $963,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory error tracking and logging2025
Memory error tracking and logging2024
Fault detecting and fault tolerant multi-threaded processors2020
Load/store unit for a processor, and applications thereof2020
Data cache virtual hint way prediction, and applications thereof2019
Load/store unit for a processor, and applications thereof2019
Processors and methods for cache sparing stores2018
Load/store unit for a processor, and applications thereof2018
Data cache virtual hint way prediction, and applications thereof2017
Data cache virtual hint way prediction, and applications thereof2015
Coherent instruction cache utilizing cache-op execution resources2013
Apparatus and method for condensing trace information in a multi-processor syste2012