Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable delay line compensated for process, voltage, and temperature

Programmable delay line compensated for process, voltage, and temperature

US Patent 7701246 · Granted Apr 20, 2010

Estimated economic value: $1,963,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Direct-bonded native interconnects and active base die2025
Direct-bonded native interconnects and active base die2023
Electronic determination of viewership by a vehicle of a media content2023
Method for combining analog neural net with FPGA routing in a monolithic integra2023
Direct-bonded native interconnects and active base die2022
Apparatus and method for combining analog neural net with FPGA routing in a mono2021
FPGA logic cell with improved support for counters2021
Direct-bonded native interconnects and active base die2020
Self healing compute array2020
Direct-bonded native interconnects and active base die2019
Enhanced memory reliability in stacked memory devices2019
Wafer testing without direct probing2019