Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio

Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio

US Patent 7668013 · Granted Feb 23, 2010

Estimated economic value: $3,868,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of manufacturing non-volatile memory device2025
Non-volatile memory device2025
Trench capacitor having improved capacitance and fabrication method thereof2023
Method for fabricating semiconductor memory device with buried capacitor and fin2023
Method of fabricating magnetic memory device2023
Physically unclonable function circuit having lower gate-to-source/drain breakdo2022
One-time programmable memory device and fabrication method thereof2022
Stacked capacitor with horizontal and vertical fin structures and method for mak2022
1.5-transistor (1.5T) one time programmable (OTP) memory with thin gate to drain2022
Semiconductor memory device with buried capacitor and fin-like electrodes2022
Magnetic memory device with multiple sidewall spacers covering sidewall of MTJ e2022
Semiconductor field programmable device2021