Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

US Patent 7667275 · Granted Feb 23, 2010

Estimated economic value: $5,706,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

IC with 3D metal-insulator-metal capacitor2023
Precision capacitor2023
Precision capacitor2023
Low temperature sub-nanometer periodic stack dielectrics2021
Precision capacitor2021
Precision capacitor2020
Plasma treatment for thin film resistors on integrated circuits2019
Capacitor with improved voltage coefficients2018
System and method for mitigating oxide growth in a gate dielectric2018
System and method for mitigating oxide growth in a gate dielectric2018
System and method for mitigating oxide growth in a gate dielectric2017
Process to enable ferroelectric layers on large area substrates2017