Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

US Patent 7580806 · Granted Aug 25, 2009

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Devices, systems, and methods for detecting and mitigating silent data corruptio2025
Devices, systems, and methods for detecting and mitigating silent data corruptio2024
Computer system and method for performing a routing supply and demand analysis d2014
Systems, methods, and computer readable media for providing instantaneous failov2013
System and method for ensuring partitioned block physical compatibility between 2013
Systems, methods, and programs for leakage power and timing optimization in inte2012
Determining the placement of semiconductor components on an integrated circuit2011
Method and apparatus for an embedded time domain reflectometry test2009
Method and apparatus for enabling a user to determine whether a defective locati2009
Circuit and method for comparing circuit performance between functional and AC s2009
Systems and methods for reconfiguring scan chains2009
Alpha-particle-tolerant semiconductor die systems, devices, components and metho2008