Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8671376 | Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process | Jason T. Gentry, Brady A. Koenig | 2014-03-11 |
| 8472311 | Systems, methods, and computer readable media for providing instantaneous failover of packet processing elements in a network | James H. Cervantes | 2013-06-25 |
| 8434052 | System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design | Brady A. Koenig, Jason T. Gentry | 2013-04-30 |
| 8332802 | Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs | Benjamin P. Haugestuen, Howard Porter | 2012-12-11 |
| 7915742 | Determining the placement of semiconductor components on an integrated circuit | Howard Porter, Troy Frerichs | 2011-03-29 |
| 7580806 | Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) | Jeffrey R. Rearick, Cory Groth | 2009-08-25 |
| 7451418 | Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size | Howard Porter, Troy Frerichs | 2008-11-11 |
| 7386824 | Determining the placement of semiconductor components on an integrated circuit | Howard Porter, Troy Frerichs | 2008-06-10 |
| 7079973 | Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) | Jeffrey R. Rearick, Cory Groth | 2006-07-18 |
| 7010641 | Integrated circuit routing resource optimization algorithm for random port ordering | Gerald L Esch, Jr. | 2006-03-07 |
| 6769104 | Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load | Scott T. Evans | 2004-07-27 |