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Home › Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process

Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process

US Patent 7575977 · Granted Aug 18, 2009

Estimated economic value: $5,910,000 ⓘ

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