Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Processor for computing a packed sum of absolute differences and packed multiply-add

Processor for computing a packed sum of absolute differences and packed multiply-add

US Patent 7516307 · Granted Apr 7, 2009

Estimated economic value: $17,723,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and system for instruction block to execution unit grouping2023
Unified register file for supporting speculative architectural states2022
Determining branch targets for guest branch instructions executed in native addr2022
Memory fragments for supporting code block execution by using virtual cores inst2021
Apparatus and method for processing an instruction matrix specifying parallel an2021
Method for implementing a line speed interconnect structure2021
Method for a delayed branch implementation by using a front end track table2021
Methods, systems and apparatus for supporting wide and efficient front-end opera2020
Method and system for implementing recovery from speculative forwarding miss-pre2020
Cache storing data fetched by address calculating load instruction with label us2020
Systems and methods for non-blocking implementation of cache flush instructions2020
Method and apparatus for nearest potential store tagging2019